The invention relates generally to electronic circuits, and more particularly to a circuit and method for providing an initial phase difference between a disk-drive read signal and a read-signal sample clock. A digital timing-recovery circuit can use this phase difference to provide an initial coarse alignment between the read signal and the sample clock. By providing an initial coarse alignment, the recovery circuit can reduce the overall alignment-acquisition time.
Switching and other types of noise can cause today""s high-speed integrated circuits (ICs) to operate improperly. One solution is to electrically isolate a noise-susceptible circuit from a noisy circuit using a ground plane, shielding, or other isolation techniques. Another solution is modify the noisy circuit so that it generates less noise.
In addition, to placate computer users who are demanding faster data-processing and data-transfer rates, IC manufacturers wish to design faster digital ICs that support these faster rates. Typically, one increases data-processing and transfer rates by increasing the clock speed of the ICs that perform these tasks. Unfortunately, merely increasing an IC""s clock frequency without redesigning it may cause circuits on the IC to oscillate.
FIG. 1 is a block diagram of a conventional disk-drive read channel 10 having a voltage-controlled oscillator (VCO) 12, which may inject noise or transients into other circuits within the read channel 10 or elsewhere. The read channel 10 includes a read path 14, which includes a disk 16 for storing data, a read head 18 for reading the disk 16 and for generating a read signal that represents the read data, a read circuit 20 for sampling the read signal in response to a sample clock, and a Viterbi detector 22 for recovering the stored data from the samples of the read signal. The read channel 10 also includes a phase-locked timing loop 24 for generating the sample clock, for aligning the sample clock with the read signal such that the read circuit 20 samples the read signal at appropriate times, and for maintaining the alignment of the sample clock. The timing loop 24 includes a phase detector 26 for generating an error signal that represents the phase difference between the read signal and the sample clock, a filter 28 for filtering the error signal, the VCO 12 for generating the sample clock at a frequency indicated by the filtered error signal, and a frequency divider 30 for allowing the frequency of the sample clock to be greater than the data rate of the read signal. The read circuit 20 effectively closes the loop 24, i.e., couples the loop input to the loop output.
FIG. 2 is a timing diagram showing the desired alignment between the sample clock and the preamble portion of the read signal. Referring to FIGS. 1 and 2, the preamble is a bit pattern stored at the beginning of every sector (individual sectors not shown) of the disk 16. The read channel 10 uses the preamble to calibrate the channel timing with respect to the read signal. While reading the preamble, the read head 18 generates a sinusoid (or an approximate sinusoid). The peaks and zero crossings of this preamble sinusoid correspond to the centers of respective data windows 34. During the subsequent data portion (not shown) of the read signal, the centers of the data windows 34 correspond to the data points of the read signalxe2x80x94the data points are the portions of the read signal that the head 18 generates while positioned directly over the respective storage locations on the surface of the disk 16. By aligning the sampling edges of the sampling clock with the peaks and zero crossings of the preamble sinusoid, these edges will be aligned with the centers of the data windows 34 during the data portion of the read signal, and thus will cause the read circuit 20 to sample the read signal at the data points.
Referring to FIGS. 1 and 2, the timing loop 24 aligns the sample clock with the read signal during the preamble portion and maintains this alignment during the data portion of the read signal. In response to the zero crossing of the preamble sinusoid at time t0, a start-up circuit (not shown) causes the VCO to generate a predetermined edge of the sample clockxe2x80x94a falling edge in this examplexe2x80x94and thus provides a coarse alignment between the preamble sinusoid and the sample clock. Next, the timing loop 24 uses negative feedback to align the rising edges of the sample clock with the sinusoid peaks and to align the falling edges of the sample clock with the sinusoid zero crossings. That is, if the rising and falling edges are leading the respective peaks and zero crossings, then the loop 24 reduces the frequency of the VCO 12. Conversely, if the rising and falling edges are lagging the respective peaks and zero crossings, then the loop 24 increases the frequency of the VCO 12. Thus, the timing loop 24 provides a fine alignment between the preamble sinusoid and the sample clock. At a predetermined time t1, the timing loop 24 is deemed to have aligned the sample clock with the preamble sinusoid. To maintain this alignment, however, the loop 24 continues to adjust the VCO frequency as necessary during the remainder of the preamble portion and throughout the data portion of the read signal.
Unfortunately, the timing loop 24 may generate noise that adversely affects other circuits such as those in the read path 14. Specifically, the adjusting of the VCO frequency to acquire and maintain alignment between the sample clock and the read signal often generates significant amounts of noise. Because the timing loop 24 is often integrated on the same die as noise-sensitive circuits, isolation techniques such as using ground plane or shielding are often unavailable, ineffective, prohibitively complex, or prohibitively expensive.
In addition, the timing loop 24 often has a relatively high latency, which often limits the data-read rate of the read channel 10. The loop""s latency is equivalent to the loop delay, or the time it takes for a signal to travel from an arbitrary starting point in the loop, through the loop, and back to the starting point. For example, starting at the output of the read circuit 20, the phase detector 26 processes a sample of the read signal, the filtered error signal adjusts the frequency of the sample clock, in response to the phase difference between the sample point of the read signal and the sample clock, the read circuit 20 generates a subsequent sample in response to the adjusted sample clock, and then the process repeats. As the frequency of the sample clock increases, the timing loop 24 effectively responds more slowly to phase changes between the read signal and sample clock, and thus the loop""s margin of stability decreases. If the frequency of the sample clock increases beyond the frequency of the loop 24, then the loop 24 oscillates and causes the read channel 10 to operate improperly. Thus, the relatively high latency of the loop 24 limits the frequency of the sample clock, and thus limits the data-read rate of the read channel 10.
Fortunately, a conventional digital timing-recovery loop does not suffer from the above-described limitations of the timing loop 24 (FIG. 1). Generally, a digital timing-recovery loop includes a free-running VCO having a frequency that corresponds to the expected rate at which the read head 18 will read data bits from the disk 16. But instead of adjusting the VCO frequency to acquire and maintain alignment between the sample clock and the read signal, the digital timing-recovery loop adjusts the values of the read samples to the values they would have had if the sample clock and read signal were aligned.
But unfortunately, using a digital timing-recovery loop instead of the phase-lock timing loop 24 (FIG. 1) often requires a reduction in the data-storage density of the disk 16 (FIG. 1). The digital timing-recovery loop lacks a start-up circuit to provide a coarse alignment between the sample clock and the read signal. Without such a start-up circuit, the digital timing-recovery loop requires a longer time to acquire alignment than the timing loop 24, and thus requires a longer preamble. Because the preamble data pattern is stored at the beginning of each sector of the disk 16, the longer the preamble, the fewer the data bits that the disk 16 can store, and thus the lower the disk""s data-storage density.
In one aspect of the invention, a circuit includes a buffer for receiving and storing two samples of a signal, and a phase calculation circuit for calculating from the samples a phase difference between one of the samples and a predetermined point of the signal.
Such a circuit can be used to decrease the alignment-acquisition time of a digital timing-recovery loop, and thus allows a shortening of the preamble and a corresponding increase in the data-storage density of a disk. In one application, the circuit determines an initial phase difference between a disk-drive read signal and a read-signal sample clock. The digital timing-recovery loop uses this phase difference to provide an initial coarse alignment between the read signal and the sample clock. By providing an initial coarse alignment, the recovery loop reduces the overall alignment-acquisition time.